Numerous applications exist in which it is desired to selectively etch metal-containing materials relative to other materials. One such application is fabrication of capacitor structures during semiconductor processing. An exemplary process for forming capacitor structures is described with reference to FIGS. 1-4.
Referring initially to FIG. 1, a semiconductor wafer fragment 10 is illustrated at a preliminary processing stage. Fragment 10 comprises a substrate 12 supporting a pair of conductive nodes 14 and 16.
Substrate 12 can comprise, for example, monocrystalline silicon lightly doped with background p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical nodes 14 and 16 can comprise, for example, conductively-doped diffusion regions extending into a monocrystalline silicon substrate. Alternatively, or additionally, the conductive nodes can comprise electrically conductive pedestals extending upwardly from conductively-doped source/drain regions, and surrounded by electrically insulative material. Substrate 12 and nodes 14 and 16 are shown diagrammatically in FIG. 1, and it is to be understood that the substrate can comprise multiple layers of material, and further that the conductive nodes 14 and 16 can comprise multiple layers of conductive material.
An electrically insulative material 18 is formed over substrate 12. Insulative material 18 can comprise any suitable electrically insulative material, or combination of electrically insulative materials. For instance, material 18 can comprise silicon dioxide, silicon nitride, doped silicon oxide (such as, for example, borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG)), etc.
A pair of openings 20 and 22 extend into insulative material 18. The openings are partially filled with a first conductive material 24 which can comprise, consist essentially of, or consist of a metal nitride, such as, for example, titanium nitride. First conductive material 24 appears to form a pair of sidewall spacers in the shown cross-sectional view. It is to be understood, however, that the openings 20 and 22 would each have a continuous periphery when viewed from above (typically a circular or elliptical periphery) and accordingly the apparent pair of spacers 24 shown within each of the openings in the cross-sectional view of FIG. 1 would actually be a single spacer extending entirely around the periphery of an opening. Material 24 can be formed in the shown configuration by depositing the material within the openings and across an upper surface of substrate 12. The deposited material will extend across bottom surfaces of the openings. The material can then be removed from over the upper surface of material 18 and from over the bottom surface of the openings with an appropriate etch, to leave the material along the sidewalls of the openings as shown.
A second conductive material 26 is formed within the openings 20 and 22 and physically against the first material 24. Second material 26 can comprise, for example, conductively-doped silicon, such as, for example, conductively-doped polycrystalline silicon. If material 26 comprises silicon, it can be undoped at the processing stage of FIG. 1. Accordingly the silicon can be electrically insulative, rather than in the shown electrically conductive form. Thus, material 26 can be a silicon material which is doped at a processing stage subsequent to that of FIG. 1, or it can be a silicon material which is doped prior to the processing stage of FIG. 1.
The wafer fragment 10 is shown divided into a first segment 30 and a second segment 32. The segments 30 and 32 can correspond to, for example, a memory array region and a region peripheral to the memory array region, respectively.
Referring to FIG. 2, first conductive material 24 (FIG. 1) is selectively etched relative to materials 26 and 18, which forms openings 36 between materials 26 and 18. If material 18 comprises silicon dioxide, silicon nitride, and/or doped oxide; material 26 comprises either doped or undoped silicon; and material 24 comprises a metal nitride (such as, for example, titanium nitride), the etching will typically be conducted with one of three etchant solutions. Such etchant solutions are: (1) sulfuric acid (H2SO4)/hydrogen peroxide (H2O2); (2) H2O2/hydrochloric acid (HCl); and (3) H2O2/ammonium hydroxide (NH4OH). The H2SO4/H2O2 solution will typically comprise a ratio of sulfuric acid (provided as a commercially available solution of sulfuric acid and water) to hydrogen peroxide (provided as commercially available hydrogen peroxide solution that is about 30 weight percent hydrogen peroxide in water) of from about 10:1 to about 2:1.
The H2O2/HCl solution will typically be formed by mixing about 5 parts water with about 1 part hydrogen peroxide (provided as commercially available hydrogen peroxide solution that is about 30 weight percent hydrogen peroxide in water) and about 1 part hydrochloric acid (provided as commercially available hydrochloric acid, which is about 29 weight percent HCl in water). The final solution will comprise about 92 weight percent water, about 4.3 weight percent hydrogen peroxide, and about 4.1 weight percent hydrochloric acid.
The H2O2/NH4OH solution will typically be formed by mixing about 10 parts water with about 1 part hydrogen peroxide (the 30 weight percent hydrogen peroxide) and about 1 part ammonium hydroxide (provided as commercially available ammonium hydroxide, which is about 29 weight percent NH4OH in water). Accordingly, the final solution will typically comprise about 95 weight percent water, about 2.5 weight percent hydrogen peroxide, and about 2.4 weight percent ammonium hydroxide.
The solutions discussed above are typically utilized at a temperature of from about 50° C. to about 75° C.
Although FIG. 2 shows the etch of the metal nitride material (24 of FIG. 1) as being highly selective relative to materials 18 and 26, such is typically not the case. Instead, some of materials 26 and 18 are removed during the etching of material 24. Removal of materials 26 and 18 decreases the height of materials 18 and 26, and can also increase the width at the upper locations of openings 36 relative to the lower locations of openings 36.
The non-selectivity of the etch becomes increasingly problematic as an aspect ratio of openings 36 increases. In modern processing, it can be desired that material 18 have a thickness of 20,000 Å or more, and that openings 36 are formed to have a width of from about 30 Å to about 150 Å. Accordingly, openings 36 are long capillaries. Etching within the capillaries is slower than etching of surfaces external to the capillaries (with the etching frequently being nearly eight-times slower in the capillaries than along surfaces external to the capillaries). Accordingly, unless the etch for the material 24 (FIG. 1) is highly selective, there will be significant loss of materials 18 and 26 during the etch. Such is a problem with conventional etching processes.
The upwardly-open structures defined by material 26 can be storage nodes for capacitor constructions. The two illustrated storage nodes are labeled as 27 and 29, respectively.
Referring to FIG. 3, the material 18 remaining after formation of openings 36 (FIG. 2) is subjected to an isotropic etch to remove the material 18 from between storage nodes 27 and 29. Since the etchant solution can penetrate into openings 36 (FIG. 2) the material 18 between structures 27 and 29 is subjected to etching from all sides during the isotropic etch, whereas the material 18 over region 32 is subjected to etching from the upper surface only. The material 18 over region 32 is thus removed more slowly than the material 18 between structures 27 and 29. Accordingly, some of material 18 remains over region 32 after removal of all of the material from between structures 27 and 29. It is desired to leave material 18 over region 32 after the isotropic etch of material 18, so that the material 18 can protect circuit device structures (not shown) associated with region 32 during subsequent processing.
The structure shown in FIG. 3 is an idealized prior art structure, and a “hoped for” structure during the processing of FIGS. 1-3. The structure can result if openings 36 (FIG. 2) have a low enough aspect ratio, so that the non-selectivity of the prior art etch does not significantly impact the height of material 18 during removal of material 24 (FIG. 1) in formation of openings 36 (FIG. 2). However, if the openings have a high enough aspect ratio, the non-selectivity of the etch will significantly reduce the height of material 18 during formation of openings 36. If the height of material 18 is reduced too much, the desired structure of FIG. 3 will not result. Instead, material 18 will be removed from over both of regions 30 and 32 during the isotropic etch of material 18.
Referring to FIG. 4, a capacitor dielectric material 40 and a second capacitor electrode 42 are formed over capacitor storage nodes 27 and 29. Capacitor dielectric material 40 can comprise any suitable material, or combination of materials, including, for example, silicon dioxide, silicon nitride, and various high-K materials. Electrode 42 can be formed of any suitable conductive material, including, for example, conductively-doped silicon, and/or various metals, and/or various metal compounds. If material 26 comprises undoped silicon at the processing stage of FIGS. 1-3, the silicon will typically be conductively-doped prior to formation of dielectric material 40 and electrode 42. Such doping can be accomplished utilizing various suitable methods including, for example, an implant directly into material 26.
Conductive material 42 is spaced from conductive material 26 by dielectric material 40, and accordingly conductive material 42, dielectric material 40 and storage nodes 27 and 29 form a pair of capacitor constructions 44 and 46. The capacitor constructions can be connected with transistor devices (not shown) and utilized as dynamic random access memory (DRAM) cells, as will be understood by persons of ordinary skill in the art. Materials 40 and 42 are not shown extending over peripheral region 32 in the shown aspect of the prior art. However, it is to be understood that the materials 40 and 42 could also be formed over peripheral region 32 in accordance with some prior art methodologies.
A difficulty in conducting the above-described prior art processing occurs during removal of material 24 (FIG. 1), and results from a lack of a suitably selective etch chemistry having a sufficiently high etch rate to perform in high aspect ratio features. It is therefore desired to develop new etch chemistries having higher selectivity for metal-containing materials (such as, for example, metal nitrides) relative to silicon nitride, silicon dioxide and/or doped silicon oxide.